The present invention relates to a process for manufacture of a semiconductor integrated circuit device and to a semiconductor integrated circuit device technology. In particular, the invention relates to a process for manufacture of a semiconductor integrated circuit device having capacitor elements for information storage and to a technology which is effective in the application of such a semiconductor integrated circuit device.
A typical example of a semiconductor integrated circuit device having capacitor elements for information storage is a DRAM (Dynamic Random Access Memory). A memory cell of a DRAM is formed of one transistor, for memory cell selection, and a capacitor (an element for information storage) which is directly connected thereto; and, therefore, the DRAM is widely used as the main memory of a variety of computers, which require a large capacity memory, and for communication apparatuses, because the integrity is high and the price per unit per bit can be inexpensive. Since a capacitor is used for an element for information storage, however, in the case that it is left as it is, a signal charge used for information storage leaks as time elapses so that the storage content is eventually lost. Therefore, in a DRAM, a so-called refreshing operation, which periodically reproduces the storage content, is required in order to maintain the information of the memory cell. Therefore, in a semiconductor integrated circuit device having a DRAM, a variety of research and substantial technological development concerning the structure and circuit arrangement have been carried out in an attempt to increase the operation speed of the entire DRAM and to increase the refreshing characteristics. As for the technology for increasing the refreshing characteristics, since the refreshing characteristics are in inverse proportion to the junction electric field intensity in the semiconductor regions for sources and drains of the transistors for memory cell selection, the optimization of the impurity concentration diffusion in the semiconductor regions for the sources and drains has been developed so as to increase the refreshing characteristics by reducing the above junction electric field intensity.
For example, in the Japanese patent Laid-Open No. 61486/1994 (U.S. Pat. No. 5,426,326), a technology is described wherein contact holes are opened in an interlayer insulating film which covers MOS (Metal Oxide Semiconductor) transistors for memory cell selection in a DRAM memory cell so that the semiconductor regions for the sources and drains are exposed, and, after that, impurities for electric field relaxation are introduced beneath the semiconductor regions for the sources and drains through the above contact holes. In addition, for example, in the Japanese patent Laid-Open No. 359842/1998, a technology is disclosed wherein impurities (boron, or the like) for controlling the threshold voltage Vth of the MOS transistors for memory cell selection are implanted only on the side to which bit lines are connected in the semiconductor substrate so as not to be implanted on the capacitor side, and, thereby, the impurity (boron, or the like) concentration of the semiconductor substrate on the capacitor side is lowered so as to lower the junction electric field intensity in the semiconductor substrate on the capacitor side.
The present inventors have, however, found that the above described technologies have the following problems.
That is to say, as the miniaturization of elements proceeds, the impurity concentration in a semiconductor substrate with respect to, for example, the element dimension is enhanced, and the side wall insulating film formed on the side walls of the gate electrodes becomes thinner, so that the gate electrodes and the semiconductor regions (high impurity concentration regions) for the sources and drains become closer in distance; and, thereby, the above described junction electric field intensity becomes larger, and, as a result, a problem arises in that the deterioration of the refreshing characteristics cannot be prevented even in the case of the use of conventional technologies. Though, in a conventional DRAM, the power consumption has been limited in order to lengthen the refreshing time when the integration is heightened, the refreshing time cannot help but be made shorter since the junction electric field intensity becomes larger when the miniaturization of the element progresses to a higher integration. As a result of this, a problem arises in that, in the case where integration continues to be heightened at the present rate, the increase in the power consumption cannot be avoided.
An object of the present invention is to provide a technology which can reduce the junction electric field intensity in the semiconductor regions for the sources and drains of field effect transistors.
Another object of the present invention is to provide a technology which can increase the driving performance of field effect transistors.
Still another object of the present invention is to provide a technology which can increase the refreshing characteristics of a semiconductor integrated circuit device.
Yet another object of the present invention is to provide a technology which can reduce power consumption of a semiconductor integrated circuit device.
Still another object of the present invention is to provide a technology which can increase the element integrity of a semiconductor integrated circuit device.
A further object of the present invention is to provide a technology which can increase the reliability of a semiconductor integrated circuit device.
An additional object of the present invention is to provide a technology which can increase the yield of a semiconductor integrated circuit device.
The above described, as well as other, objects and novel characteristics of the present invention will be clarified through the description provided in this specification and the attached drawings.
A summary of a representative aspect of the invention which is disclosed in the present application will be briefly described as follows.
That is to say, the present invention provides the step of forming first trenches in a semiconductor substrate, the step of forming isolation parts by filling in said first trenches with an insulating film, the step of forming trenches for forming wires so as to overlap, in a plane manner, said isolation parts and active regions which are surrounded by said isolation parts, the step of forming an isolation film inside the trenches for forming said wires and the step of forming wires inside of said trenches for forming wires via said isolation film inside trenches, wherein in said step of forming trenches for forming wires, the corners of the bottom are rounded, and in said step of forming an isolation film inside the trenches part of, or all of, the insulating film is formed inside of the trenches through a deposition method.
In addition, the present invention provides the step of forming first trenches in a semiconductor substrate, the step of forming isolation parts by filling in said first trenches with an insulating film, the step of forming a mask having aperture parts including part of, both, of said isolation parts and active regions surrounded by said isolation parts on the semiconductor substrate, the step of forming third trenches by forming second trenches by removing the insulating film of the isolation parts which are exposed from said aperture parts and, after that, by removing the semiconductor substrate part which is exposed from said aperture parts, and the step of forming wires inside said second and third trenches.
In addition, the present invention provides first trenches formed in a semiconductor substrate, isolation parts formed by filling in said trenches with an insulating film, trenches for forming wires formed so as to overlap, in a plane manner, said isolation parts and active regions which are surrounded, in a plane manner, by said isolation parts, an insulating film inside the trenches formed inside said trenches for forming wires and wires formed inside said trenches for forming wires via the isolation film inside the trenches, wherein said insulating film inside the trenches has an insulating film formed through deposition and the corners of the bottom inside said trenches for forming wires are rounded.
In addition, in accordance with the present invention, said step of forming trenches for forming wires includes a step of creating the trenches, a step of oxidizing the inner surface of the trenches and a step of removing the oxide film formed through the above oxidization step.
In addition, in accordance with the present invention, the radius of curvature of the angles of the bottom inside said trenches for forming wires has a value which doesn""t exceed a predetermined value of a sub-threshold coefficient of field effect transistors, of which the gate electrodes are said wires.
In addition, in accordance with the present invention, the radius of curvature of the angles of the bottom inside said trenches for forming said wires is 10 nm or more.
In addition, in accordance with the present invention, forward tapers are formed on the side surfaces of said trenches for forming wires.
In addition, in accordance with the present invention, said trenches for forming wires are formed so that the width of the aperture parts is wider than the width of the bottoms.
In addition, in accordance with the present invention, said step of forming the trenches for forming wires has the step of forming a mask having aperture parts including part of, both, of said isolation parts and active regions which are surrounded by said isolation parts on the semiconductor substrate, the step of forming the second trenches by removing the insulating film of the isolation parts which is exposed from said aperture parts and the step of forming the third trenches by removing the semiconductor substrate parts which are exposed from said aperture parts.
In addition, in accordance with the present invention, said step of forming the trenches for forming wires includes the step of forming a mask which has aperture parts including part of, both, of said isolation parts and active regions which are surrounded by said isolation parts and the step of forming the third trenches by forming the second trenches by removing the insulating film of isolation parts which is exposed from said aperture parts and, after that, by removing the semiconductor substrate parts which are exposed from said aperture parts and the second trenches.
In addition, in accordance with the present invention, said step of forming the trenches for forming wires has the step of forming said third trenches deeper than the second trenches and the step of oxidizing the inside of said third trenches and, after that, removing the oxide film.
In addition, in accordance with the present invention, at the time of forming said second trenches, the insulating film of isolation parts remains at the bottoms of the second trenches so that a parasitic element is not, finally, formed in the lower part of the wires.
In addition, in accordance with the present invention, the thickness of the insulating film of the isolation parts which remains at the bottoms of said second trenches is 100 nm or more.
In addition, in accordance with the present invention, the depth of said first trenches finally becomes deeper than that of said second and third trenches.
In addition, in accordance with the present invention, said step of forming an insulating film inside the trenches includes the step of forming an insulating film by oxidizing the semiconductor substrate which is exposed from said trenches for forming wires, and the step of forming an insulating film through a deposition method.
In addition, in accordance with the present invention, said wires are made of metal and the insulating film, formed through a deposition method, which is said insulating film inside the trenches, is made of silicon nitride.
In addition, in accordance with the present invention, said step of forming wires has the step of filling in the inside of said second and third trenches with the first film, the step of removing said first film so that part of the first film remains within said second and third trenches and the step of filling in the recesses of the top surface of the first film within said second and third trenches with the second film.
In addition, the present invention has the step of further removing said first film so that part of the first film remains within said second and third trenches after the recesses on the top surface of said first film are filled in with a second film.
In addition, in accordance with the present invention, said wires are made of a metal or a compound of metal and silicon.
In addition, in accordance with the present invention, said wires are made of a metal and the insulating film formed through a deposition method of said insulating film within the trenches is made of silicon nitride.
In addition, the method of the present invention includes, after said step of forming wires, the step of forming a cap insulating film on the wires inside said trenches for forming wires.
In addition, the method of the present invention includes, after forming said cap insulating film, the step of depositing an insulating film on said semiconductor substrate, the step of opening holes in said insulating film from which said active regions are exposed, the step of filling in said holes with a conductive film and the step of forming semiconductor regions in the active regions by diffusing impurities to the semiconductor substrate from said conductive film.
In addition, in accordance with present invention, said step of forming holes includes the step of applying an etching treatment under conditions where the etching rate is faster in said insulating film than in the cap insulating film.
In addition, in accordance with the present invention, said insulating film of isolation parts is formed of silicon oxide while said cap insulating film is formed of silicon nitride.
In addition, in accordance with the present invention, the thickness of said cap insulating film is 40 nm or more.
In addition, in accordance with the present invention, said insulating film of isolation parts is formed of silicon oxide, said cap insulating film is formed of silicon nitride and said insulating film on the semiconductor substrate is formed of silicon oxide.
In addition, the method of the present invention includes, after said step of forming wires, the step of forming semiconductor regions for the sources and drains of field effect transistors of which the gate electrodes are the wires on both sides of the wires, in a plane manner, in said semiconductor substrate.
In addition, in accordance with the present invention, the height of the top surface of said gate electrodes is lower than the height of said trenches for forming wires and of the main surface of the semiconductor substrate where the first trenches are not formed.
In addition, in accordance with the present invention, said gate electrodes are spaced away from high concentration regions wherein the impurity concentration is relatively high in said semiconductor regions for the sources and drains.
In addition, in accordance with the present invention, the distance between said gate electrodes and said high concentration regions is 40 nm or more.
In addition, in accordance with the present invention, said gate electrodes and said high concentration regions wherein the impurity concentration is comparatively high in said semiconductor regions for the sources and drains are spaced from each other, and low concentration regions where the impurity concentration is comparatively low in said semiconductor regions for the sources and drains are formed deeper than the top surface of said gate electrodes.
In addition, in accordance with the present invention, said field effect transistors form transistors for memory cell selection and a capacitor element for information storage is electrically connected to one of said semiconductor regions for the sources and drains.
In addition, the semiconductor integrated circuit device of the present invention has trenches created in a semiconductor substrate, first semiconductor regions which are formed to extend up to a position deeper than said trenches in said semiconductor substrate, a gate insulating film formed inside said trenches, gate electrodes formed inside said trenches via the gate insulating film, and semiconductor regions for the sources and drains formed on both sides of said gate electrodes, in a plane manner, in the semiconductor substrate, wherein said semiconductor regions for the sources and drains are formed to extend up to a position shallower than said first semiconductor regions, and second semiconductor regions, of which the conductivity type is opposite to that of said first semiconductor regions, and third semiconductor regions, of which the conductivity type is same as that of said second semiconductor regions, are formed to extend up to a position shallower than said second semiconductor regions, and the impurity concentration of said third semiconductor regions is higher than the impurity concentration of said second semiconductor regions.
In addition, in accordance with the present invention, borders between said second semiconductor regions and third semiconductor regions are formed at positions shallower than the top surface of said gate electrodes.
In addition, in accordance the present invention, the distance between said borders and said gate electrodes is 40 nm or more.
In addition, in accordance with the present invention, borders between said first semiconductor regions and said second semiconductor regions are formed at positions deeper than the top surface of said gate electrodes.
In addition, in accordance with the present invention, a cap insulating film is formed on said gate electrodes inside said trenches.
In addition, in accordance with the present invention, the thickness of said cap insulating film on the gate electrodes is 40 nm or more.
In addition, in accordance with the present invention, said cap insulating film on the gate electrodes is made of silicon nitride.
In addition, in accordance with the present invention, said gate electrodes are made of metal or a silicide film of metal and said gate insulating film has an insulating film formed through a deposition method.
In addition, in accordance with the present invention, said gate insulating film formed through a deposition method is made of silicon nitride.
In addition, the semiconductor integrated circuit device of the present invention has a plurality of memory cells formed of field effect transistors having said gate electrodes and capacitor elements for information storage which are electrically connected to one of said semiconductor regions for the sources and drains.
In addition, in accordance with the present invention, said semiconductor regions for the sources and drains to which the capacitor elements for information storage are connected are formed to be deeper than the other semiconductor regions for the sources and drains.
In addition, in accordance with the present invention, field effect transistors in a peripheral circuit region of a memory region formed of said memory cells have a buried gate electrode structure, and the semiconductor regions for the sources and drains of the field effect transistors of the buried gate electrode structure in said peripheral circuit region are formed to be deeper than the semiconductor regions for the sources and drains of the field effect transistors of said memory cells.